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19-3661; Rev 1; 8/05
KIT ATION EVALU E AILABL AV
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
General Description
The MAX5066 is a two-phase, configurable single- or dual-output buck controller with an input voltage range of 4.75V to 5.5V or from 5V to 28V. Each phase of the MAX5066 is designed for 180 operation. A mode pin allows for a dual-output supply or connecting two phases together for a single-output, high-current supply. Each output channel of the MAX5066 drives n-channel MOSFETs and is capable of providing more than 25A of load current. The MAX5066 uses average current-mode control with a switching frequency up to 1MHz per phase where each phase is 180 out of phase with respect to the other. Out-of-phase operation results in significantly reduced input capacitor ripple current and output voltage ripple in dual-phase, single-output voltage applications. Each buck regulator output has its own highperformance current and voltage-error amplifier that can be compensated for optimum output filter L-C values and transient response. The MAX5066 offers two enable inputs with accurate turn-on thresholds to allow for output voltage sequencing of the two outputs. The device's switching frequency can be programmed from 100kHz to 1MHz with an external resistor. The MAX5066 can be synchronized to an external clock. Each output voltage is adjustable from 0.61V to 5.5V. Additional features include thermal shutdown, "hiccup mode" short-circuit protection. Use the MAX5066 with adaptive voltage positioning for applications that require a fast transient response, or accurate output voltage regulation. The MAX5066 is available in a thermally enhanced 28-pin TSSOP package capable of dissipating 1.9W. The device is rated for operation over the -40C to +85C extended, or -40C to +125C automotive temperature range. 4.75V to 5.5V or 5V to 28V Input Dual-Output Synchronous Buck Controller Configurable for Two Separate Outputs or One Single Output Each Output is Capable of Up to 25A Output Current Average Current-Mode Control Provides Accurate Current Limit 180 Interleaved Operation Reduces Size of Input Filter Capacitors Limits Reverse Current Sinking When Operated in Parallel Mode Each Output is Adjustable from 0.61V to 5.5V Independently Programmable Adaptive Voltage Positioning Independent Shutdown for Each Output 100kHz to 1MHz per Phase Programmable Switching Frequency Oscillator Frequency Synchronization from 200kHz to 2MHz Hiccup Mode Overcurrent Protection Overtemperature Shutdown Thermally Enhanced 28-Pin TSSOP Package Capable of Dissipating 1.9W Operates Over -40C to +85C or -40C to +125C Temperature Range
Features
MAX5066
Ordering Information Applications
High-End Desktop Computers Graphics Cards Networking Systems Point-of-Load High-Current/High-Density Telecom DC-DC Regulators RAID Systems
PART MAX5066EUI MAX5066AUI TEMP RANGE -40C to +85C -40C to +125C PIN-PACKAGE 28 TSSOP-EP* 28 TSSOP-EP*
*Exposed Pad
________________________________________________________________ Maxim Integrated Products
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
ABSOLUTE MAXIMUM RATINGS
IN to AGND.............................................................-0.3V to +30V BST_ to AGND........................................................-0.3V to +35V DH_ to LX_ ....................................-0.3V to (VBST_ - VLX_) + 0.3V DL_ to PGND ..............................................-0.3V to (VDD + 0.3V) BST_ to LX_ ..............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V AGND to PGND .....................................................-0.3V to +0.3V REG, RT/CLKIN, CSP_, CSN_ to AGND ..................-0.3V to +6V All Other Pins to AGND ............................-0.3V to (VREG + 0.3V) REG Continuous Output Current (Limited by Power Dissipation, No Thermal or Short-Circuit Protection).........................................................................67mA REF Continuous Output Current ........................................200A Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 23.8mW/C above +70C) .....1904mW Package Thermal Resistance (JC) ...................................2C/W Operating Temperature Ranges MAX5066EUI ...................................................-40C to +85C MAX5066AUI .................................................-40C to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS 5 Input Voltage Range Quiescent Supply Current REG Undervoltage Lockout Hysteresis REG Output Accuracy REG Dropout INTERNAL REFERENCE Internal Reference Voltage Internal Reference Voltage Accuracy Accuracy Load Regulation MOSFET DRIVERS p-Channel Output Driver Impedance n-Channel Output Driver Impedance Output Driver Source Current Output Driver Sink Current Nonoverlap Time (Dead Time) RON_P RON_N IDH_, IDL_ IDH_, IDL_ tNO CDH_ or CDL_ = 5nF 1.35 0.45 2.5 8 30 4 1.35 A A ns VEAN_ VEAN_ EAN_ connected to EAOUT_ (Note 2) VIN = VREG = 4.75V to 5.5V or VIN = 5V to 28V, EAN_ connected to EAOUT_ (Note 2) IREF = 100A IREF = 0 to 200A -0.9 0.6135 +0.9 V % VIN IIN UVLO VHYST VIN = 5.8V to 28V, ISOURCE = 0 to 65mA VIN < 5.8V, ISOURCE = 60mA 4.75 IN and REG shorted together for +5V operation fOSC = 500kHz, DH_, DL_ = open VREG rising 4.0 4.75 4 4.15 200 5.10 5.30 0.5 28 5.5 20 4.5 V mA V mV V V SYMBOL CONDITIONS MIN TYP MAX UNITS
STARTUP/INTERNAL REGULATOR OUTPUT (REG)
EXTERNAL REFERENCE VOLTAGE OUTPUT (REF) VREF 3.23 3.2 3.3 3.37 3.4 V V
2
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25C.) (Note 1)
PARAMETER OSCILLATOR 1MHz (max) switching frequency per phase RRT = 12.4k RRT = 127k -7.5 -10 1.225 0.5 2.4 0.8 30 200 2000 1000 kHz 100 +7.5 +10 % V mA V V ns kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5066
Switching Frequency
fSW
Switching Frequency Accuracy RT/CLKIN Output Voltage RT/CLKIN Current Sourcing Capability RT/CLKIN Logic-High Threshold RT/CLKIN Logic-Low Threshold RT/CLKIN High Pulse Width RT/CLKIN Synchronization Frequency Range CURRENT LIMIT Average Current-Limit Threshold Reverse Current-Limit Threshold Cycle-by-Cycle Current-Limit Threshold Cycle-by-Cycle Current-Limit Response Time DIGITAL FAULT INTEGRATION (DF_) Number of Switching Cycles to Shutdown in Current-Limit Number of Switching Cycles to Recover from Shutdown CURRENT-SENSE AMPLIFIER CSP_ to CSN_ Input Resistance Common-Mode Range Input Offset Voltage Amplifier Gain -3dB Bandwidth CSP_ Input Bias Current RCS_ VCMR(CS) VOS(CS) AV(CS) f-3dB ICSA(IN) NSDF_ NRDF_ VCL_ VRCL_ VCLpk_ tR VRT/CLKIN IRT/CLKIN VRT/CLKIN_H VRT/CLKIN_L tRT/CLKIN fRT/CLKIN
fSW = 250kHz nominal, RRT = 50k fSW = 1MHz nominal, RRT = 12.4k
VCSP_ - VCSN_ VCSP_ - VCSN_ VCSP_ - VCSN_
20.4 -3.13
22.5 -1.63 52.5 260
24.75 -0.1
mV mV mV ns
32,768 524,288
Clock cycles Clock cycles k +3.6 +5.5 V V V V/V MHz 120 30 A
1.9835 VIN = VREG = 4.75V to 5.5V or VIN = 5V to 10V VIN = 7V to 28V -0.3 -0.3 100 36 4 VCSP_ = 5.5V, sinking VCSP_ = 0V, sourcing
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25C.) (Note 1)
PARAMETER Transconductance Open-Loop Gain Open-Loop Gain Unity-Gain Bandwidth EAN_ Input Bias Current Error Amplifier Output Clamping High Voltage Error Amplifier Output Clamping Low Voltage EN_ INPUTS EN_ Input High Voltage EN_ Hysteresis EN_ Input Leakage Current MODE INPUT MODE Logic-High Threshold MODE Logic-Low Threshold MODE Input Pulldown THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis TSHDN THYST 160 10 C VMODE_H VMODE_L IPULLDWN 5 2.4 0.8 V V A IEN -1 VENH EN rising 1.204 1.222 0.05 +1 1.240 V A SYMBOL gM AVOL(CEA) AVOL(EA) fUGEA IBIAS(EA) VCLMP_HI
(EA)
CONDITIONS
MIN
TYP 550
MAX
UNITS S dB dB MHz nA V V
CURRENT-ERROR AMPLIFIER (CEA_) No load 50 70 3 VEAN_ = 2.0V With respect to VCM With respect to VCM 100 1.14 -0.234
VOLTAGE ERROR AMPLIFIER (EAOUT_)
VCLMP_LO
(EA)
Note 1: The device is 100% production tested at TA = +85C (MAX5066EUI) and TA = TJ = +125C (MAX5066AUI). Limits at -40C and +25C are guaranteed by design. Note 2: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage accuracy must include external resistor-divider tolerances.
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Typical Operating Characteristics
(Circuit of Figure 6, TA = +25C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY (VIN = 5V)
MAX5066 toc01
OSCILLATOR FREQUENCY vs. RT
10,000 OSCILLATOR FREQUENCY (kHz) CDH = CDL = 0 16 14 SUPPLY CURRENT (mA) 12 10 8 6 4 2 10 0 100 200 300 400 500 600 700 800 900 1000 RT (k) 0
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY (VIN = 12V)
CDH = CDL = 0 fSW = 1MHz 14 SUPPLY CURRENT (mA) 12 10 8 6 4 2 0 fSW = 125kHz fSW = 250kHz fSW = 500kHz
MAX5066 toc02b MAX5066 toc02a
CDH = CDL = 0
fSW = 1MHz fSW = 500kHz
16
1000
fSW = 250kHz fSW = 125kHz
100
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY (VIN = 24V)
MAX5066 toc02c
SUPPLY CURRENT vs. OSCILLATOR FREQUENCY
MAX5066 toc03
SUPPLY CURRENT vs. DRIVER LOAD CAPACITANCE
90 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 0 CLOAD = CDH = CDL
MAX5066 toc04
16 14 SUPPLY CURRENT (mA) 12 10 8 6 4 2 0
CDH = CDL = 0
fSW = 1MHz
14 CDH_ = CDL_ = 0 13 SUPPLY CURRENT (mA) 12 11 10 9 8 7 6 VIN = 5V VIN = 24V VIN = 12V
100
fSW = 500kHz
fSW = 250kHz fSW = 125kHz
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (kHz)
0
5
10
15 CLOAD (nF)
20
25
30
REG LOAD REGULATION
MAX5066 toc05
REG LINE REGULATION
MAX5066 toc06
REF LOAD REGULATION
MAX5066 toc07
5.10 VIN = 24V
5.10 5.08 5.06 VREG (V) IREG = 0
3.305
5.05 VREG (V)
3.300 VIN = 24V VREF (V)
5.00 VIN = 5.5V 4.95
VIN = 12V
5.04 5.02 5.00 IREG = 60mA 4.98
3.295 VIN = 5V 3.290
VIN = 12V
4.90 0 10 20 30 40 50 60 70 80 90 100 IREG (mA)
4.96 5 7 9 11 13 15 17 19 21 23 VIN (V)
3.285 0 100 200 300 400 500 600 700 800 IREF (A)
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
REF LINE REGULATION
MAX5066 toc08
DRIVER RISE TIME vs. LOAD CAPACITANCE
MAX5066 toc09
DRIVER FALL TIME vs. LOAD CAPACITANCE
35 DH 30 DL tFALL (ns) 25 DL 20 15 10 5 0
MAX5066 toc10
3.303 3.302 IREF = 0 3.301 3.300 3.299 3.298 3.297 3.296 5 7 9 11 13 15 17 19 21 23 VIN (V) IREF = 200A
100 90 80 70 tRISE (ns) 60 50 40 30 20 10 0 0 2 4 6 DH
40
VREF (V)
8 10 12 14 16 18 20 22 CLOAD (nF)
0
2
4
6
8 10 12 14 16 18 20 22 CLOAD (nF)
HIGH-SIDE DRIVER RISE TIME (VIN = 12V, CLOAD = 10nF)
MAX5066 toc11
HIGH-SIDE DRIVER FALL TIME (VIN = 12V, CLOAD = 10nF)
MAX5066 toc12
DH_ 2V/div
DH_ 2V/div
20ns/div
20ns/div
LOW-SIDE DRIVER RISE TIME (VIN = 12V, CLOAD = 10nF)
MAX5066 toc13
DL_ 2V/div
20ns/div
6
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
LOW-SIDE DRIVER FALL TIME (VIN = 12V, CLOAD = 10nF)
MAX5066 toc14
OUT1/OUT2 OUT-OF-PHASE WAVEFORMS (VOUT1 = 0.8V, VOUT2 = 1.3V)
MAX5066 toc15
LX1 10V/div OUT1 100mV/div
DL_ 2V/div
LX2 10V/div OUT2 100mV/div 20ns/div 10s/div
TURN-ON/-OFF WAVEFORMS (IOUT1 = IOUT2 = 10A)
SHORT-CIRCUIT CURRENT WAVEFORMS (VIN = 5V)
MAX5066 toc17
MAX5066 toc16
VOUT1 1V/div
IOUT1 10A/div
EN1 5V/div VOUT2 1V/div EN2 5V/div 2ms/div 200ms/div
IOUT2 10A/div
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Pin Description
PIN 1 NAME CSN2 FUNCTION Current-Sense Differential Amplifier Negative Input for Output2. Connect CSN2 to the negative terminal of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-sense amplifier (AV(CS) = 36V/V). Current-Sense Differential Amplifier Positive Input for Output2. Connect CSP2 to the positive terminal of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-sense amplifier (AV(CS) = 36V/V). Voltage Error-Amplifier Output2. Connect to an external gain-setting feedback resistor. The erroramplifier gain determines the output voltage load regulation for adaptive voltage positioning. This output also serves as the compensation network connection from EAOUT2 to EAN2. A resistive network results in a drooped output voltage regulation characteristic. An integrator configuration results in very tight output voltage regulation (see the Adaptive Voltage Positioning section). Voltage Error-Amplifier Inverting Input for Output2. Connect a resistive divider from VOUT2 to EAN2 to AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A resistive network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage regulation (see the Adaptive Voltage Positioning section). Current-Error Amplifier Output2. Compensate the current loop by connecting an R-C network from CLP2 to AGND. 3.3V Reference Output. Bypass REF to AGND with a minimum 0.1F ceramic capacitor. REF can source up to 200A for external loads. External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to AGND to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency synchronization. Analog Ground Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck regulator. When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see Figure 1) and the device operates as a two-output, out-of-phase buck regulator. When MODE is connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2. Current-Error Amplifier Output1. Compensate the current loop by connecting an R-C network from CLP1 to AGND. Voltage Error Amplifier Inverting Input for Output1. Connect a resistive divider from VOUT1 to EAN1 to regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight output voltage regulation (see the Adaptive Voltage Positioning section). Voltage Error Amplifier Output1. Connect to an external gain-setting feedback resistor. The error amplifier gain determines the output-voltage-load regulation for adaptive voltage positioning. This output also serves as the compensation network connection from EAOUT1 to EAN1. A resistive network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage regulation (see the Adaptive Voltage Positioning section). Current-Sense Differential Amplifier Positive Input for Output1. Connect CSP1 to the positive terminal of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-sense amplifier (AV(CS) = 36V/V).
2
CSP2
3
EAOUT2
4
EAN2
5 6
CLP2 REF
7 8
RT/CLKIN AGND
9
MODE
10
CLP1
11
EAN1
12
EAOUT1
13
CSP1
8
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
Pin Description (continued)
PIN 14 NAME CSN1 FUNCTION Current-Sense Differential Amplifier Negative Input for Output1. Connect CSN1 to the negative terminal of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-sense amplifier (AV(CS) = 36V/V). Output 1 Enable. A logic-low shuts down channel 1's MOSFET drivers. EN1 can be used for output sequencing. Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver supply. Connect a 0.47F ceramic capacitor between BST1 and LX1. High-Side Gate Driver Output1. DH1 drives the gate of the high-side MOSFET. External inductor connection and source connection for the high-side MOSFET for Output1. LX1 also serves as the return terminal for the high-side MOSFET driver. Low-Side Gate Driver Output1. Gate driver output for the synchronous MOSFET. Supply Voltage for Low-Side Drivers. REG powers VDD. Connect a parallel combination of 0.1F and 1F ceramic capacitors from VDD to PGND and a 1 resistor from VDD to REG to filter out the highpeak currents of the driver from the internal circuitry. Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias circuitry. Bypass REG to AGND with a 4.7F ceramic capacitor. Supply Voltage Connection. Connect IN to a 5V to 28V input supply. Power Ground. Source connection for the low-side MOSFET. Connect VDD's bypass capacitor returns to PGND. Low-Side Gate Driver Output2. Gate driver for the synchronous MOSFET. External inductor connection and source connection for the high-side MOSFET for Output2. Also serves as the return terminal for the high-side MOSFET driver. High-Side Gate Driver Output2. DH2 drives the gate of the high-side MOSFET. Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver supply. Connect a 0.47F ceramic capacitor between BST2 and LX2. Output 2 Enable. A logic-low shuts down channel 2's MOSFET drivers. EN2 can be used for output sequencing. Exposed Pad. Connect exposed pad to ground plane.
MAX5066
15 16 17 18 19 20
EN1 BST1 DH1 LX1 DL1 VDD
21 22 23 24 25 26 27 28 EP
REG IN PGND DL2 LX2 DH2 BST2 EN2 EP
Detailed Description
The MAX5066 switching power-supply controller can be configured in two ways. With the MODE input high, it operates as a single-output, dual-phase, step-down switching regulator where each output is 180 out of phase. With the MODE pin connected low, the MAX5066 operates as a dual-output, step-down switching regulator. The average current-mode control topology of the MAX5066 offers high-noise immunity while having benefits similar to those of peak current-mode control. Average current-mode control has the intrinsic ability to accurately limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the error amplifier output voltage
(EAOUT1 or EAOUT2) that connects to the positive input of the transconductance amplifier (CA1 or CA2) is clamped thus limiting the output current. The MAX5066 contains all blocks necessary for two independently regulated average current-mode PWM regulators. It has two voltage error amplifiers (VEA1 and VEA2), two current-error amplifiers (CEA1 and CEA2), two current-sensing amplifiers (CA1 and CA2), two PWM comparators (CPWM1 and CPWM2), and drivers for both low- and high-side power MOSFETs (see Figure 1). Each PWM section is also equipped with a pulse-by-pulse, current-limit protection and a fault integration block for hiccup protection.
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
CLP1 10 EAOUT1 EAN1 12 11 VEA1 IN 22 VREG = 5V UVLO 2VP-P RAMP CEA1 CPWM1 DF1 AND HICCUP LOGIC
13 CSP1 CA1 14 CSN1
16 BST1 17 DH1 CONTROL AND DRIVER LOGIC 1 18 LX1 20 VDD 19 DL1 0
REG EN1
21 15
FOR INTERNAL BIASING CEN1 1.225V VREF = 3.3V UV33 THERMAL SHUTDOWN
REF
6
OSCILLATOR AND PHASE SPLITTER
EXTERNAL FREQUENCY SYNC
7 RT/CLKIN
VINTREF = 0.61V EN2 28
1.225V CEN2 2VP-P RAMP
180
27 BST2 26 DH2 CONTROL AND DRIVER LOGIC 2 25 LX2 VDD 24 DL2
AGND
8
VEA2 EAN2 EAOUT2 MODE CLP2 4 3 9 5
MUX CEA2
CPWM2
23 PGND
DF2 AND HICCUP LOGIC CA2
2 CSP2 1 CSN2
Figure 1. Block Diagram
Two enable comparators (CEN1 and CEN2) are available to control and sequence the two PWM sections through the enable (EN1 or EN2) inputs. An oscillator, with an externally programmable frequency generates two clock pulse trains and two ramps for both PWM sections. The two clocks and the two ramps are 180 out of phase with each other. A linear regulator (REG) generates the 5V to supply the device. This regulator has the output-current capability
10
necessary to provide for the MAX5066's internal circuitry and the power for the external MOSFET's gate drivers. A low-current linear regulator (REF) provides a precise 3.3V reference output and is capable of driving loads of up to 200A. Internal UVLO circuitry ensures that the MAX5066 starts up only when VREG and VREF are at the correct voltage levels to guarantee safe operation of the IC and of the power MOSFETs.
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
Finally, a thermal-shutdown feature protects the device during thermal faults and shuts down the MAX5066 when the die temperature exceeds +160C. diodes D1 and D2 (see Figure 6). Connect a 0.1F ceramic capacitor between BST_ and LX_. Minimize the trace inductance from BST_ and VDD to rectifier diodes, D1 and D2, and from BST_ and LX_ to the boost capacitors, C8 and C9 (see Figure 6). This is accomplished by using short, wide trace lengths.
MAX5066
Dual-Output/Dual-Phase Select (MODE)
The MAX5066 can operate as a dual-output independently regulated buck converter, or as a dual-phase, single-output buck converter. The MODE input selects between the two operating modes. When MODE is grounded (logic low), VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see Figure 1) and the device operates as a two-output DC-DC converter. When MODE is connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2 and the device works as a dual-phase, single-output buck regulator with each output 180 out of phase with respect to each other.
Undervoltage Lockout (UVLO)/ Power-On Reset (POR)/Soft-Start
The MAX5066 includes an undervoltage lockout (UVLO) with hysteresis, and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO threshold monitors VREG and is internally set between 4.0V and 4.5V with 200mV of hysteresis. Hysteresis eliminates "chattering" during startup. Most of the internal circuitry, including the oscillator, turns on when V REG reaches 4.5V. The MAX5066 draws up to 4mA (typ) of current before VREG reaches the UVLO threshold. The compensation network at the current-error amplifiers (CLP1 and CLP2) provides an inherent soft-start of the output voltage. It includes (R14 and C10) in parallel with C11 at CLP1 and (R15 and C12) in parallel with C13 at CLP2 (see Figure 6). The voltage at the currenterror amplifier output limits the maximum current available to charge the output capacitors. The capacitor at CLP_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage.
Supply Voltage Connections (VIN/VREG)
The MAX5066 accepts a wide input voltage range at IN of 5V to 28V. An internal linear regulator steps down VIN to 5.1V (typ) and provides power to the MAX5066. The output of this regulator is available at REG. For VIN = 4.75V to 5.5V, connect IN and REG together externally. REG can supply up to 65mA for external loads. Bypass REG to AGND with a 4.7F ceramic capacitor for highfrequency noise rejection and stable operation. REG supplies the current for both the MAX5066's internal circuitry and for the MOSFET gate drivers (when connected externally to VDD), and can source up to 65mA. Calculate the maximum bias current (IBIAS) for the MAX5066: IBIAS = IIN + fSW x (QGQ1 + QGQ2 + QGQ3 + QGQ4 ) where IIN is the quiescent supply current into IN (4mA, typ), Q GQ1 , Q GQ2 , Q GQ3 , Q GQ4 are the total gate charges of MOSFETs Q1 through Q4 at VGS = 5V (see Figure 6), and fSW is the switching frequency of each individual phase.
Setting the Switching Frequency (fSW)
An internal oscillator generates the 180o out-of-phase clock signals required for both PWM modulators. The oscillator also generates the 2VP-P voltage ramps necessary for the PWM comparators. The oscillator frequency can be set from 200kHz to 2MHz by an external resistor (RT) connected from RT/CLKIN to AGND (see Figure 6). The equation below shows the relationship between RT and the switching frequency: fOSC = 2.5 x 1010 Hz RRT
Low-Side MOSFET Driver Supply (VDD)
VDD is the power input for the low-side MOSFET drivers. Connect the regulator output REG externally to VDD through an R-C lowpass filter. Use a 1 resistor and a parallel combination of 1F and 0.1F ceramic capacitors to filter out the high peak currents of the MOSFET drivers from the sensitive internal circuitry.
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side MOSFET drivers for output 1 and output 2, respectively. Connect BST1 and BST2 to V DD through rectifier
where RRT is in ohms and fSW(PER PHASE) = fOSC/2. Use RT/CLKIN as a clock input to synchronize the MAX5066 to an external frequency (fRT/CLKIN). Applying an external clock to RT/CLKIN allows each PWM section to work at a frequency equal to fRT/CLKIN/2. An internal comparator with a 1.6V threshold detects fRT/CLKIN. If fRT/CLKIN is present, internal logic switches from the internal oscillator clock, to the clock present at RT/CLKIN.
11
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Hiccup Fault Protection
The MAX5066 includes overload fault protection circuitry that prevents damage to the power MOSFETs. The fault protection consists of two digital fault integration blocks that enable "hiccuping" under overcurrent conditions. This circuit works as follows: for every clock cycle the current-limit threshold is exceeded, the fault integration counter increments by one count. Thus, if the current-limit condition persists, then the counter reaches its shutdown threshold in 32,768 counts and shuts down the external MOSFETs. When the MAX5066 shuts down due to a fault, the counter begins to count down, (since the current-limit condition has ended), once every 16 clock cycles. Thus, the device counts down for 524,288 clock cycles. At this point, switching resumes. This produces an effective duty cycle of 6.25% power-up and 93.75% power-down under fault conditions. With a switching frequency set to 250kHz, power-up and power-down times are approximately 131ms and 2.09s, respectively. loop consists of an inner current loop and an outer voltage loop. The inner current loop controls the output current, while the outer voltage loop controls the output voltage. The inner current loop absorbs the inductor pole, reducing the order of the outer voltage loop to that of a single-pole system. Figure 2 is the block diagram of OUT1's control loop. The current loop consists of a current-sense resistor, RSENSE, a current-sense amplifier (CA1), a currenterror amplifier (CEA1), an oscillator providing the carrier ramp, and a PWM comparator (CPWM1). The precision current-sense amplifier (CA1) amplifies the sense voltage across RSENSE by a factor of 36. The inverting input to CEA1 senses the output of CA1. The output of CEA1 is the difference between the voltageerror amplifier output (EAOUT1) and the gained-up voltage from CA1. The RC compensation network connected to CLP1 provides external frequency compensation for the respective CEA1 (see the Compensation section). The start of every clock cycle enables the high-side driver and initiates a PWM oncycle. Comparator CPWM1 compares the output voltage from CEA1 against a 0 to 2V ramp from the
Control Loop
The MAX5066 uses an average current-mode control topology to regulate the output voltage. The control
CSN1 CA 1
CSP1
RCF
CCF
CLP1
CCFF
VIN
RF
CEA1 CPWM1 DRIVE
IL
RSENSE
VOUT1
VEA1
2VP-P
R1 COUT LOAD R2
VREF = 0.61V
Figure 2. Current and Voltage Loops 12 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
oscillator. The PWM on-cycle terminates when the ramp voltage exceeds the error voltage from the current-error amplifier (CEA1). The outer voltage control loop consists of the voltageerror amplifier (VEA1). The noninverting input (EAN1) is externally connected to the midpoint of a resistive voltage-divider from OUT1 to EAN1 to AGND. The voltage loop gain is set by using an external resistor from the output of this amplifier (EAOUT1) to its inverting input (EAN1). The noninverting input of (VEA1) is connected to the 0.61V internal reference.
Voltage Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the voltage control loop. Its output clamps to 1.14V and -0.234V relative to VCM = 0.61V. Set the MAX5066 output voltage by connecting a voltage-divider from the output to EAN_ to GND (see Figure 4). At no load the output of the voltage error amplifier is zero. Use the equation below to calculate the no load voltage: R VOUT(NL) = 0.6135 x 1 + 1 R2 The voltage at full load is given by: R VOUT(FL) = 0.6135 x 1 + 1 - VOUT R2 where V OUT is the voltage-positioning window described in the Adaptive Voltage Positioning section.
MAX5066
Peak-Current Comparator
The peak-current comparator (see Figure 3) monitors the voltage across the current-sense resistor (RSENSE) and provides a fast cycle-by-cycle current limit with a threshold of 52.5mV. Note that the average current-limit threshold of 22.5mV still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output inductor with a saturation current specification greater than the average current limit of 22.5mV/RSENSE. Proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a damaged output inductor. The typical propagation delay of the peak current-limit comparator is 260ns.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques to reduce cost, size, and power dissipation. Voltage positioning (Figure 5) reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. A larger allowed voltage-step excursion reduces the required number of output capacitors and/or allows the use of higher ESR capacitors. The internal 0.61V reference in the MAX5066 has a tolerance of 0.9%. If we use 0.1% resistors for R1 and R2, we still have another 4% available for the variation in the output voltage from nominal. This available voltage range allows us to reduce the total number of output capacitors to meet a given transient response requirement. This results in a voltage-positioning window as shown in Figure 5. From the allowable voltage-positioning window we can calculate the value of RF from the equation below. I x RSENSE x 36 x R1 RF = OUT VOUT where VOUT is the allowable voltage-positioning window, RSENSE is the sense resistor, 36 is the currentsense amplifier gain, and R1 is as shown in Figure 4.
Current-Error Amplifier
The MAX5066 has two dedicated transconductance current-error amplifiers CEA1 and CEA2 with a typical gM of 550S and 320A output sink and source capability. The current-error amplifier outputs (CLP1 and CLP2) serve as the inverting input to the PWM comparators. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (see CCFF, CCF, and RCF in Figure 2). Compensate the current-error amplifier such that the inductor current down slope, which becomes the up slope at the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the duty cycle for each cycle by comparing the currenterror amplifier output to a 2VP-P ramp. At the start of each clock cycle an R-S flip-flop resets and the highside drivers (DH1 and DH2) turn on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the current-error amplifier output voltage, thus terminating the on cycle.
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13
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
VDD
PEAK-CURRENT COMPARATOR 52.5mV CLP_ CSP_ CSN_ GMIN RAMP 2 x fSW (V/S) CLK 1.225V EN_ PGND R Q LX_ DL_ AV = 36 gM = 500S PWM COMPARATOR S Q BST_ DH_
Figure 3. Current Comparator and MOSFET Driver Logic
VOUT
VOLTAGE-POSITIONING WINDOW
VCNTR + VOUT/2
RF R1 COUT LOAD R2 VREF = 0.61V EAN_ EAOUT_
VCNTR
VCNTR - VOUT/2
NO LOAD
1/2 LOAD LOAD (A)
FULL LOAD
Figure 4. Voltage Error Amplifier
Figure 5. Defining the Voltage-Positioning Window
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side drivers (DL1 and DL2) drive the gates of external n-channel MOSFETs. The high-peak sink and source current capability of these drivers provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced switching losses. For low14
output, voltage-regulating applications where the duty cycle is less than 50%, choose high-side MOSFETs (Q2 and Q4, Figure 6) with a moderate RDS(ON) and a very low gate charge. Choose low-side MOSFETs (Q1 and Q3, Figure 6) with very low RDS(ON) and moderate gate charge. The driver block also includes a logic circuit that provides an adaptive nonoverlap time (30ns typical) to
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
VIN
VDD D1 (100mA, 30V) C2 1F Q2 IRF7821 L1 0.5H C8 0.1F Q1 IRF7832 DH1 LX1 22 BST1
IN
REG
C5 10F R3 1 D2 (100mA, 30V) C3 0.1F C4 4.7F
22 BST2 Q4 IRF7821 DH2 LX2 Q3 IRF7832
0.8V/10A
R1 2m
C9 0.1F
L2 0.8H
MAX5066
C6 680F D3 (1A, 30V) DL1 DL2
R2 2m
1.3V/10A
D4 (1A, 30V)
C7 680F
R4 1.74k CSP1 CSN1 EAN1 R5 4.64k EAOUT1 R8 29.4k VREG OR VREF R16 100k EN1 C14 0.1F EN2 C15 0.1F
PGND
CSP2 CSN2 EAN2 EAOUT2 MODE R9 60.4k
R6 5.11k
R7 4.75k
R14 1k CLP1 C11 120pF R15 1k CLP2
C10 15nF
R17 100k
C12 15nF
RT/CLKIN
REF
AGND
C13 120pF
RT 24.9k EXTERNAL FREQUENCY SYNC
C1 0.22F
Figure 6. Dual-Output Buck Regulator
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15
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
VIN
VDD D1 (100mA, 30V) C2 1F C8 0.1F Q1 IRF7832 22 BST1 Q2 IRF7821 L1 0.8H DH1 LX1
IN
REG
C5 10F R3 1 D2 (100mA, 30V) C3 0.1F C4 4.7F
22 BST2 Q4 IRF7821 DH2 LX2
1.3V/20A
R1 2m
C9 0.1F
L2 0.8H
MAX5066
C6 680F D3 (1A, 30V) DL1 DL2
Q3 IRF7832 D4 (1A, 30V)
R2 2m
R4 5.11k CSP1 CSN1 EAN1 EAOUT1 R8 60.4k VREG OR VREF R16 100k EN1 C14 0.1F
PGND
CSP2 CSN2 EAN2 EAOUT2 MODE TO REG
R5 4.75k
R14 1k CLP1 C11 120pF
C10 15nF
R17 100k
EN2 C15 0.1F CLP2
R15 1k
C12 15nF
RT/CLKIN
REF
AGND
C13 120pF
RT 24.9k EXTERNAL FREQUENCY SYNC
C1 0.22F
Figure 7. Dual-Phase, Single-Output Buck Regulator
16
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
prevent shoot-through currents during transition. Figure 7 shows the dual-phase, single-output buck regulator. inductor with a saturating current greater than the worst-case peak inductor current: IL _ PEAK = 24.75 x 10 -3 IL + RSENSE 2
MAX5066
Design Procedures
Inductor Selection
The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable voltage ripple at the output, determine the inductance value. Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency due to the charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs. The situation worsens at higher input voltages, since capacitive switching losses are proportional to the square of the input voltage. Lower switching frequencies on the other hand will increase the peak-to-peak inductor ripple current (IL) and therefore increase the MOSFET conduction losses (see the Power MOSFET Selection section for a detailed description of MOSFET power loss). When using higher inductor ripple current, the ripple cancellation in the multiphase topology, reduces the input and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value: L= VOUT (VIN(MAX) - VOUT ) VIN x fSW x IL
where 24.75mV is the maximum average current-limit threshold for the current-sense amplifier and RSENSE is the sense resistor.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate charge, R DS(ON) , power dissipation, the maximum drain-to-source voltage, and package thermal impedance. The product of the MOSFET gate charge and onresistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5066's output is proportional to the total capacitance it drives at DH1, DH2, DL1, and DL2. The power dissipated in the MAX5066 is proportional to the input voltage and the average drive current. See the Supply Voltage Connection (V IN /V REG ) and the Low-Side MOSFET Drives Supply (VDD) sections to determine the maximum total gate charge allowed from all driver outputs together. The losses may be broken into four categories: conduction loss, gate drive loss, switching loss and output loss. The following simplified power loss equation is true for both MOSFETs in the synchronous buck-converter:
PLOSS = PCONDUCTION + PGATEDRIVE + PSWITCH + POUTPUT
Choose IL to be equal to about 30% of the output current per channel. Since IL affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material for custom inductors. High IL causes large peak-to-peak flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with high IL, reduces the required minimum inductance and even makes the use of planar inductors possible. The advantages of using planar magnetics include low-profile design, excellent current sharing between phases due to the tight control of parasitics, and low cost. For example, the minimum inductance at VIN = 12V, VOUT = 0.8V, IL = 3A, and fSW = 500kHz is 0.5H. The average current-mode control feature of the MAX5066 limits the maximum inductor current, which prevents the inductor from saturating. Choose an
For the low-side MOSFET, the PSWITCH term becomes virtually zero because the body diode of the MOSFET is conducting before the MOSFET is turned on. Tables 1 and 2 describe the different losses and shows an approximation of the losses during that period.
Input Capacitance
The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source, dictate the capacitance requirement. Increasing the number of phases increases the effective switching frequency and lowers the peak-to-average current ratio, yielding lower input capacitance requirement. It can be shown that the
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17
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Table 1. High-Side MOSFET Losses
LOSS DESCRIPTION SEGMENT LOSS
Conduction Loss
Losses associated with MOSFET on-time and on-resistance. IRMS is a function of load current and duty cycle.
PCONDUCTION = IRMS 2 x RDS(ON) where IRMS VOUT x ILOAD VIN
Gate Drive Loss
Losses associated with charging and discharging the gate capacitance of the MOSFET every cycle. Use the MOSFET's (QG) specification. Losses during the drain voltage and drain current transitions for every switching cycle. Losses occur only during the QGS2 and QGD time period and not during the initial QGS1 period. The initial QGS1 period is the rise in the gate voltage from zero to VTH. RDH is the high-side MOSFET driver's onresistance and RGATE is the internal gate resistance of the high-side MOSFET (QGD and QGS2 are found in the MOSFET data sheet). Losses associated with QOSS of the MOSFET occur every cycle when the high-side MOSFET turns on. The losses are caused by both MOSFETs but are dissipated in the high-side MOSFET.
PGATEDRIVE = VDD x QG x fSW
PSWITCH = VIN x ILOAD x fSW x
(QGS2 + QGD ) IGATE
Switching Loss
where IGATE =
VDD 2 x (RDH + RGATE )
Output Loss
POUTPUT =
QOSS(HS) + QOSS(LS) x VIN x fSW 2
worst-case RMS current occurs when only one controller section is operating. The controller section with the highest output power needs to be used in determining the maximum input RMS ripple current requirement. Increasing the output current drawn from the other outof-phase controller section results in reducing the input ripple current. A low-ESR input capacitor that can handle the maximum input RMS ripple current of one channel must be used. The maximum RMS capacitor ripple current is given by: ICIN(RMS) IMAX VOUT (VIN - VOUT ) VIN
Output Capacitors
The worst-case peak-to-peak inductor ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. The output ripple can be approximated as the inductor current ripple multiplied by the output capacitor's ESR (RESR_OUT). The peak-to-peak inductor current ripple is given by: V (1 - D) IL = OUT L x fSW During a load step, the allowable deviation of the output voltage during the fast transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE ) depends on the closed-loop bandwidth of the regulator. The resistive drop across the capacitor's ESR and capacitor discharge causes a voltage drop during a
where I MAX is the full load current of the regulator. VOUT is the output voltage of the same regulator and CIN is C5 in Figure 6. The ESR of the input capacitors wastes power from the input and heats up the capacitor. Reducing the ESR is important to maintain a high overall efficiency and in reducing the heating of the capacitors.
18
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Table 2. Low-Side MOSFET Losses
LOSS DESCRIPTION SEGMENT LOSSES
PCONDUCTION = IRMS 2 x RDS(ON)
Conduction Loss Losses associated with MOSFET on-time, IRMS is a function of load current and duty cycle.
where IRMS
VIN - VOUT x ILOAD VIN
Gate Drive Loss
Losses associated with charging and discharging the gate of the MOSFET every cycle. There is no QGD charging involved in this MOSFET due to the zero-voltage turn-on. The charge involved is (QG - QGD).
PGATEDRIVE = VDD x (QG - QGD ) x fSW
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver's resistance and the MOSFET's internal gate resistance.
load step. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output-voltage deviation less than or equal to the adaptive voltage-positioning window (VOUT). During a load step, assume a 50% contribution each from the output capacitance discharge and the voltage drop across the ESR (VOUT = VESR_OUT + VQ_OUT). Use the following equations to calculate the required ESR and capacitance value: RESR _ OUT = COUT = VESR _ OUT ILOAD _ STEP VQ _ OUT
Due to tolerances involved, the minimum average voltage at which the voltage across the current-sense resistor is clamped is 20.4mV. Therefore, the minimum average current limit is set at: ILIMIT(MIN) = 20.4 x 10 -3 RSENSE
For example, the current-sense resistor: 20.4mV RSENSE = = 2.04m 10A for a maximum output current of 10A. The standard value is 2m. Also, adjust the value of the currentsense resistor to compensate for parasitics associated with the PC board. Select a noninductive resistor with appropriate wattage rating. The second type of current limit is the peak current limit as explained in the Peak-Current Comparator section. The third current-protection circuit is the hiccup fault protection as explained in the Hiccup Fault Protection section. The average current during a short at the output is given by: IAVG(SHORT) = 1.41 x 10 -3 RSENSE
ILOAD _ STEP x tRESPONSE
where I LOAD_STEP is the step in load current and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth. COUT is C6 and C7 in Figure 6.
Current Limit
The average current-mode control technique of the MAX5066 accurately limits the maximum average output current per phase. The MAX5066 senses the voltage across the sense resistor and limits the maximum inductor current accordingly. Use the equations below to calculate the current-sense resistor values: 24.75 x 10 -3 RSENSE
Reverse Current Limit
The MAX5066 limits the reverse current when the output capacitor voltage is higher than the preset output voltage. Calculate the maximum reverse current limit based on VCLAMP_LO and the current-sense resistor RSENSE.
ILOAD(MAX) =
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19
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
1.63 x 10 -3 IREVERSE = RSENSE For stability of the current loop, the amplified inductorcurrent downslope at the negative input of the PWM comparator (CPWM1 and CPWM2) must not exceed the ramp slope at the comparator's positive input. This puts an upper limit on the current-error amplifier gain at the switching frequency. The inductor current downslope is given by VOUT/L where L is the value of the inductor (L1 and L2 in Figure 6) and VOUT is the output voltage. The amplified inductor current downslope at the negative input of the PWM comparator is given by: VL VOUT = x RSENSE x 36 x gM x RCF t L where RSENSE is the current-sense resistor (R1 and R2 in Figure 6) and gM x RCF is the gain of the current-error amplifier (CEA_) at the switching frequency. The slope of the ramp at the positive input of the PWM comparator is 2V x fSW. Use the following equation to calculate the maximum value of RCF (R14 or R15 in Figure 6). RCF 2 x fSW x L VOUT x RSENSE x 36 x gM (1)
MAX5066
Output-Voltage Setting
The output voltage is set by the combination of resistors R1, R2, and RF as described in the Voltage Error Amplifier section. First select a value for resistor R2. Then calculate the value of R1 from the following equation: R1 = (VOUT(NL) - 0.6135) 0.6135 x R2
where VOUT(NL) is the voltage at no load. Then find the value of RF from the following equation: I x RSENSE x 36 x R1 RF = OUT VOUT where VOUT is the allowable drop in voltage from no load to full load. RF is R8 and R9, R1 is R4 and R6, R2 is R5 and R7 in Figure 6.
Compensation
The MAX5066 uses an average current-mode control scheme to regulate the output voltage (see Figure 2). The main control loop consists of an inner current loop and an outer voltage loop. The voltage error amplifier (VEA1 and VEA2) provides the controlling voltage for the current loop in each phase. The output inductor is "hidden" inside the inner current loop. This simplifies the design of the outer voltage control loop and also improves the power-supply dynamics. The objective of the inner current loop is to control the average inductor current. The gain-bandwidth characteristic of the current loop can be tailored for optimum performance by the compensation network at the output of the currenterror amplifier (CEA1 or CEA2). Compared with peak current-mode control, the current-loop gain crossover frequency, fC, can be made approximately the same, but the gain at low frequencies is much higher. This results in the following advantages over peak currentmode control. 1) The average current tracks the programmed current with a high degree of accuracy. 2) Slope compensation is not required, but there is a limit to the loop gain at the switching frequency in order to achieve stability. 3) Noise immunity is excellent. 4) The average current-mode method can be used to sense and control the current in any circuit branch.
20
The highest crossover frequency fCMAX is given by: f x VIN fCMAX = SW 2 x VOUT or alternatively: f x 2 x VOUT fSW = CMAX VIN Equation (1) can now be rewritten as: RCF = x fC x L VIN x RS x 9 x gM (2)
In practical applications, pick the crossover frequency (fC) in the range of: fSW f < fC < SW . 10 2 First calculate RCF in equation 2 above. Calculate CCF such that: 10 CCF = 2 x x fC x RCF where CCF is C10 and C12 in Figure 6.
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Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Calculate CCFF such that: CCFF = 1 2 x x fC x 10 x RCF 8) Distribute the power components evenly across the top side for proper heat dissipation. 9) Keep AGND and PGND isolated and connect them at one single point close to the IC. Do not connect them together anywhere else. 10) Place all input bypass capacitors for each input as close to each other as is practical.
where CCFF is C11 and C13 in Figure 6.
Applications Information
Independant Turn-On and Off
The MAX5066 can be used to regulate two outputs from one controller. Each of the two outputs can be turned on and off independently of one another by controlling the enable input of each phase (EN1 and EN2). A logic-low on each enable pin shuts down the MOSFET drivers for that phase. When the voltage on the enable pin exceeds 1.2V, the drivers are turned on and the output can come up to regulation. This method of turning on the outputs allows the MAX5066 to be used for power sequencing.
Pin Configuration
TOP VIEW
CSN2 1 CSP2 2 EAOUT2 3 EAN2 4 CLP2 5 REF 6 RT/CLKIN 7 AGND 8 MODE 9 CLP1 10 EAN1 11 EAOUT1 12 CSP1 13 CSN1 14 *EXPOSED PADDLE 28 EN2 27 BST2 26 DH2 25 LX2 24 DL2
MAX5066
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low losses, low output noise, and clean and stable operation. This is especially true for dual-phase converters where one channel can affect the other. Use the following guidelines for PC board layout: 1) Place the V DD , REG, and the BST1 and BST2 bypass capacitors close to the MAX5066. 2) Minimize all high-current switching loops. 3) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PC boards (2oz or higher) to enhance efficiency and minimize trace inductance and resistance. 4) Run the current-sense lines CSP_ and CSN_ very close to each other to minimize loop areas. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of the current-sense resistors. 5) Place the bank of output capacitors close to the load. 6) Isolate the power components on the top side from the analog components on the bottom side with a ground plane in between. 7) Provide enough copper area around the switching MOSFETs, inductors, and sense resistors to aid in thermal dissipation and reducing resistance.
23 PGND 22 IN 21 REG 20 VDD 19 DL1 18 LX1 17 DH1 16 BST1 15 EN1
TSSOP
*CONNECT EXPOSED PAD TO GROUND PLANE.
Chip Information
TRANSISTOR COUNT: 6252 PROCESS: BiCMOS
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21
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications MAX5066
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
XX XX
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD
21-0108
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
TSSOP 4.4mm BODY.EPS

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